A transistor is generally formed by a self-aligned polysilicon gate process wherein a source/drain is formed adjacent to a gate by an ion implantation process using the gate as a mask. The source/drain is thereby self-aligned to a gate electrode of the gate. A channel region directly under the gate is also defined by the gate electrode. In order to reduce hot electron injection into the channel region, a source/drain dopant is implanted into a recess adjacent the gate. This lightly doped region is commonly referred to as a lightly doped drain region. The gate serves as a mask for the implant and the source/drain dopant tends to diffuse under a portion of the gate during subsequent thermal processing thereof. Thus, the lightly doped drain region is located adjacent and underlies a portion of the gate. Thereafter, spacers are formed alongside the gate electrode and another source/drain dopant is implanted to form the source/drain. The main section of the source/drain is laterally spaced away from an edge of the gate by the spacer thickness. The source/drain, therefore, consists of a main doped portion to which an external contact is made and the lightly doped drain region adjacent the channel region.
In accordance with a trend toward higher packaging density, transistor features are becoming increasingly smaller resulting in a shorter channel region. A shorter channel region, however, can lead to short channel effects that affect the device performance. In conventional lightly doped drain processes, short channel effects are compensated by implanting shallower junctions which come at the expense of high impurity concentrations. As a consequence, the resultant lower impurity concentrations cause undesirably high source and drain series resistance. There have been several attempts in the past to form improved shallow, lightly doped drain regions. For instance, U.S. Pat. No. 6,627,502 entitled “Method for Forming High Concentration Shallow Junctions for Short Channel MOSFETs,” issued Sep. 30, 2003, to Cho, which is commonly assigned with the present invention and incorporated herein by reference, provides a lightly doped drain region by forming shallow lightly doped drain diffusions using polysilicon sidewalls as a diffusion source. Cho and many others continue to investigate processes that provide improved shallow, lightly doped drain regions.
Additionally, as the source/drain is formed in contact with a substrate, a P-N junction is formed within the transistor. At the P-N junction, holes from P-side diffuse into the N-side, while electrons from N-side diffuse into the P-side. As a consequence, an internal field is built, and an electrically neutral depletion region is formed therebetween. The depletion region plays a role as a dielectric layer between the gate and source/drain electrodes which causes a junction capacitance.
A magnitude of the junction capacitance depends on a width of the depletion regions, and the width of depletion regions is related to a junction profile of the implanted ions in the substrate. Because of an abrupt junction profile of arsenic ions, for instance, the width of the depletion region is narrow, and the junction capacitance may become large. Additionally, the high energy implanted arsenic ions create defects in the silicon crystal structure of the substrate, which can lead to leakage in the source/drain.
Analogous to the continuous efforts to develop new processes for the lightly doped drain regions, there have been attempts in the past to reduce junction capacitance associated with the gate and source/drain electrodes of the transistor. For instance, U.S. Pat. No. 6,274,448 entitled “Method of suppressing junction capacitance of source/drain regions,” issued Aug. 14, 2001 to Lin, et al, which is incorporated by reference, discloses a method of suppressing junction capacitance associated with a transistor. The source/drains are formed by double implantation of phosphorus ions and arsenic ions. The phosphorus ion implantation lowers an energy needed in the implantation of arsenic ions and reduces dislocations in the source/drains formed during the implantation of the arsenic ions. Further, the double implantation suppresses a junction profile of the arsenic ions and enhances the width of depletion regions. As a result, the junction capacitance is reduced, thereby accelerating a function of the transistor. (Abstract of Lin, et al.). While Lin, et al. provides a solution to lowering a junction capacitance associated with a transistor, there is still a need in the art to provide other processes and structures that reduce a junction capacitance thereof.
Accordingly, what is needed in the art is a transistor and related process of forming the transistor that overcomes short channel effects while at the same time reducing a junction capacitance thereof that improves upon or resolves the deficiencies in the prior art.